Home Page
» Online Library » Implementing Sticky Bit Generators Based on FPGA Carry-Chains for Floating-Point Adders
Implementing Sticky Bit Generators Based on FPGA Carry-Chains for Floating-Point Adders
| Theme: | ||
| Author: | Чиркова Елена Владимировна (with the team of authors) | |
| Annotation: | When performing addition or subtraction in the floating point format, the sticky bit is used in some rounding modes. To generate the sticky bit, the multiple-input OR gate is required. If addition or subtraction is implemented in FPGA, the sticky bit generation can slow down the work of the adder. This paper proposes the sticky bit generators based on FPGA carry-chains. The proposed generators are intended for those adders which work with normalized numbers of single and double precision (according to IEEE 754 standard). The specific feature of the generators is that they work simultaneously but are not integrated with shifters involved in the alignment of the summands. This paper assesses resource utilization and performance of the proposed sticky bit generators; evaluates the contributions to the sticky bit generation delay of FPGA logic elements and routing resources used in the generators’ circuits. | |
| Type: | Article | |
| Kind: | Electronic edition | |
| Parts: | 1 | |
| The year of publishing: | 2020 | |
| Publishing house: | Springer | |
| The target audience: | Researcher | |
| Special purpose: | Informational | |
| Copyright holder: | Ушенина Инна Владимировна, Пензенский Государственный Технологический Университет | |
| Url: | https://link.springer.com/chapter/10.1007/978-3-030-51974-2_2 | |
| Language: | English | |
| Post date: | 23.11.2020 |